This application claims the benefit of Korean Application Nos. 97-35754, filed on Jul. 29, 1997 and 98-1472, filed Jan. 20, 1998, which are hereby incorporated by reference.
1. Field of Invention
The present invention relates to a thin film transistor (TFT), liquid crystal display (LCD) and fabricating methods thereof, and more particularly a TFT having source/drain lines on which an insulating layer and an active layer are located and lie on an insulated substrate.
2. Discussion of Related Art
FIGS. 1A to 1 E show cross-sectional views of a method of fabricating a TFT having coplanar structure and LCD having a storage capacitor according to first prior art.
Referring to FIG. 1A, a buffer layer 11 is deposited on a glass substrate 100 of an insulated substrate. In this case, the buffer layer 11 prevents impurities of the glass substrate 100 from penetrating into a silicon layer during the crystallization of amorphous silicon by both depositing and annealing amorphous silicon. Then, an active layer 12 is formed by etching a crystallized amorphous silicon layer, which is crystallized by laser annealing after the amorphous silicon layer has been deposited on the first insulating layer 11 through photolithography. To form a first storage electrode 12T of a storage capacitor, a selective impurity doping process is carried out by using a photoresist pattern PR on the active layer 12.
Referring to FIG. 1B, a second insulating layer and a conductive layer are formed in turn on the disclosed surface. A second storage electrode 14T corresponding to the gate electrode 14G and a gate line (not shown in the drawing) is formed by etching the conductive layer. A gate insulating layer 13 is formed by etching the second insulating layer by using the second storage electrode 14T as a mask.
Referring to FIG. 1C, a source region 12S and a drain region 12D are formed in the active layer 12 by doping the entire disclosed surface with impurity. In this case, the gate electrode 14G defines a channel region 12C which is under the gate electrode 14G and in the active layer 12 by blocking impurity, wherein the drain region 12D is connected to the first storage electrode 12T.
Referring to FIG. 1D, a third insulating layer 15 is formed on the entire disclosed surface. A first contact hole disclosing the source and drain region 12S and 12D of the active layer 12 is formed by etching the third insulating layer 15 through photolithography. After another conductive layer has been deposited on the entire disclosed surface, a source electrode 16S connected to the source region 12S, a data line (not shown in the drawing) and a drain electrode 16D are formed by etching the conductive layer through photolithography.
Referring to FIG. 1E, a fourth insulating layer is deposited on the entire disclosed surface. A second contact hole disclosing the drain electrode 16D is formed by etching the fourth insulating layer 17 through photolithography. Then, a transparent conductive layer is deposited on the entire disclosed surface. A pixel electrode 18 connected to the drain electrode 16D is formed by etching the transparent conductive layer through photolithography.
As explained above, the first prior art requires a step of depositing an insulating layer for forming a buffer layer in order to prevent impurities of a glass substrate from penetrating into a silicon layer during the crystallization of amorphous silicon by depositing and annealing amorphous silicon. The step of depositing the insulating layer is complicated and increases the manufacturing cost. Moreover, the above step also requires two photolithography processes to form two contact holes. The photolithography prosess is carried out by a series of complicated and fine steps, such as masking, applying photoresist, performing exposure and development, which affects productivity and integrity of the product. A major factor in the LCD production is the simplification of fabricating process by means of reducing the number of such photo-etch and the steps of forming insulating layers.
FIG. 2 shows a cross-sectional view of TFT having a staggered structure according to second prior art.
A source electrode 21S and a drain electrode 21D are formed on an insulated substrate 200 and then an active layer 23 is formed connected to the electrodes 21S and 21D. The active layer may be formed by the following steps of depositing an amorphous silicon layer on an entire disclosed surface, crystallizing the amorphous silicon layer by laser annealing and etching the crystallized silicon layer. A source region 23S and a drain region 23D are formed in the active layer 23 by an impurity-doping process after a gate insulating layer 24 and a gate electrode 25 have been formed in turn on a certain part of the active layer 23. An insulating layer 26 then covers the entire disclosed surface. A contact hole disclosing the drain region 23D is formed in the insulating layer 26. A pixel electrode 27 connected to the drain region 23D is formed on the insulating layer 26.
In the above-mentioned second prior art, an amorphous silicon layer is crystallized by annealing after the amorphous silicon layer covering the electrodes of source 21S and drain 21D have been deposited. Accordingly, the step or height difference increases when the thickness of the source and the drain electrodes are increased in order to reduce resistance of a conductive line. So a silicon layer on the part of the step might become open or exposed when the amorphous silicon is abnormally deposited on the electrodes or laser-annealed. Moreover, the crystal characteristics of a part where silicon contacts with a metal electrode are inferior to that of the other part where silicon is intact. Hence, the current characteristic of TFT is rendered inferior.
Accordingly, the present invention is directed to a TFT, LCD and fabricating methods that substantially obviate one or more of the problems due to limitations and disadvantages of the prior art.
The object of the present invention is to provide a TFT having a structure of BBC (Buried Bus Coplanar) by forming a source/drain line on a substrate and by forming a buffer layer which covers the source/drain line and is required for the crystallization of silicon, simplifying the process by means of reducing the deposition steps which are fewer than in prior art. The BBC structure of the TFT has a source/drain line on a substrate, an insulating layer covering the source/drain line and the entire disclosed surface and a coplanar structure on the insulating layer.
Another object of the present invention is to provide a data line in the TFT of the BBC structure having low resistance applicable to a wide-screen by means of increasing the thickness of both the buffer layer and the source/drain line.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a thin film transistor of the invention includes a substrate, a source and a drain electrode on the substrate, a buffer layer covering the source and the drain electrodes and a disclosed surface, an active layer on the buffer layer wherein the active layer has a source region, a channel region and a drain region, a gate insulating layer on the active layer, and a gate electrode on the gate insulating layer.
In another aspect of the present invention, a liquid crystal display includes an insulated substrate, a data line on the insulated substrate, a buffer layer covering the data line, an active layer on the buffer layer, wherein the active layer has source, channel and drain regions, a insulating layer covering the active layer, a gate electrode overlapped with the channel region, a gate line connected to the gate electrode, wherein the gate line crosses with the data line, a passivation layer covering the gate electrode and the gate line, a first contact hole in the first, the second or the passivation layer, wherein the first contact hole discloses a portion of the data line, a second contact hole disclosing the source region, a third contact hole disclosing the drain region, a connecting wire connecting the data line to the source region through the first and second contact hole, and a pixel electrode connected to the drain region through the third contact hole.
In another aspect of the present invention, a method of fabricating thin film transistor includes the steps of forming source and drain electrodes on a substrate, forming an insulating layer covering the source and the drain electrodes and a disclosed surface, forming an active layer on the insulating layer, forming a gate insulating layer and a gate electrode on a certain part of the active layer, and forming source and drain regions in the active layer by means of doping the active layer selectively with impurity.
In a further aspect of the present invention, a method of fabricating liquid crystal display includes the steps of forming a data line on an insulated substrate, forming a buffer layer covering the data line, forming an active layer on the buffer layer, forming a insulating layer covering the active layer, forming a gate line in said active layer, wherein the gate line is connected to the gate electrode and the gate electrode and crosses with the data line, forming a source region, a channel region and a drain region in the active layer by doping the active layer with impurity by using the gate electrode as a mask, forming a passivation layer covering the active layer, the gate electrode and the gate line, forming a first contact hole disclosing a portion of the data line, forming a second contact hole disclosing the source region, forming a third contact hole disclosing the drain region, forming a connecting wire connecting a disclosed portion of the data line to the disclosed source region through the first and the second contact hole, and forming a pixel electrode connected to the drain region through the third contact hole.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.